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EL7585A
Data Sheet September 21, 2005 FN7523.2
TFT-LCD Power Supply
The EL7585A represents a multiple output regulators for use in all large panel, TFT-LCD applications. It features a single boost converter with integrated 3.5A FET, two positive LDOs for VON and VLOGIC generation, and a single negative LDO for VOFF generation. The boost converter can be programmed to operate in either P-mode or PI-mode for improved load regulation. The EL7585A also integrates fault protection for all four channels. Once a fault is detected, the device is latched off until the input supply or EN is cycled. This device also features an integrated start-up sequence for VBOOST, VOFF, then VON or for VOFF, VBOOST, and VON sequencing. The latter requires a single external transistor. The timing of the start-up sequence is set using an external capacitor. The VLOGIC output is constantly enabled, but does shut down when a fault condition is detected. The EL7585A is specified for operation over the -40C to +85C temperature range.
Features
* 3.5A current limit FET options * 3V to 5V input * Up to 20V boost out * 1% regulation on all outputs * VOFF-VBOOST-VON or VBOOST-VOFF-VON sequence control - VLOGIC is on from start-up for EL7585A * Programmable sequence delay * Fully fault protected * Thermal shutdown * Internal soft-start * 20 Ld QFN packages * Pb-free plus anneal available (RoHS compliant)
Applications
* LCD monitors (15"+) * LCD-TV (up to 40"+) * Notebook displays (up to 16") * Industrial/medical LCD displays
Pinout
EL7585A (20 LD QFN) TOP VIEW
17 SGND 19 VDD 16 FBB 20 PG 18 EN
Ordering Information
15 CINT
CDLY 1 DELB 2 LX1 3 LX2 4 DRVP 5 SGND 9 DRVN 10 FBP 6 DRVL 7 FBL 8 THERMAL PAD
PART NUMBER
14 VREF 13 PGND 12 PGND 11 FBN
PART MARKING
PACKAGE
TAPE & REEL 7" 13"
PKG. DWG. # MDP0046 MDP0046 MDP0046
EL7585AILZ (Note) EL7585AILZ-T7 (Note)
EL7585AIL Z 20 Ld 4x4 QFN (Pb-free) EL7585AIL Z 20 Ld 4x4 QFN (Pb-free)
EL7585AILZ-T13 EL7585AIL Z 20 Ld 4x4 QFN (Note) (Pb-free)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
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CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
EL7585A
Absolute Maximum Ratings (TA = 25C)
VDRVP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36V VDRVN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20V VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5V VDELB, VLX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24V VDRVL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.5V Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +150C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40C to +85C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Maximum continuous junction temperature . . . . . . . . . . . . . . 125C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER SUPPLY VS IS CLOCK FOSC BOOST VBOOST VFBB VF_FBB VREF CREF DMAX ILXMAX ILEAK rDS(ON) Eff I(VFBB) VBOOST/ VIN VBOOST/ IBOOST VBOOST/ IBOOST VCINT_T VON LDO VFBP VF_FBP IFBP GMP Supply Voltage Quiescent Current
VDD = 5V, VBOOST = 11V, ILOAD = 200mA, VON = 15V, VOFF = -5V, VLOGIC = 2.5V, over temperature from -40C to 85C, unless otherwise specified. CONDITION MIN TYP MAX UNIT
DESCRIPTION
3 Enabled, LX not switching Disabled 1.7 700
5.5 2.5 900
V mA A
Oscillator Frequency
900
1000
1100
kHz
Boost Output Range Boost Feedback Voltage TA = 25C
5.5 1.192 1.188 1.205 1.205 0.9 TA = 25C 1.19 1.187 1.215 1.215 100
20 1.218 1.222
V V V V
FBB Fault Trip Point Reference Voltage
1.235 1.238
V V nF %
VREF Capacitor Maximum Duty Cycle Switch Current Limit Switch Leakage Current Switch On-Resistance Boost Efficiency Feedback Input Bias Current Line Regulation Load Regulation - "P" mode Load Regulation - "PI" mode CINT Pl Mode Select Threshold See curves Pl mode, VFBB = 1.35V CINT = 4.7nF, IOUT = 100mA, VIN = 3V to 5.5V CINT pin strapped to VDD, 50mA < ILOAD < 250mA CINT = 4.7nF, 50mA < IO < 250mA VLX = 16V
22 85
3.5 10 160 92 50 0.05 3 0.1 4.7 4.8 500
A A m % nA %/V % % V
FBP Regulation Voltage
IDRVP = 0.2mA, TA = 25C IDRVP = 0.2mA VFBP falling VFBP = 1.35V VDRVP = 25V, IDRVP = 0.2 to 2mA
1.176 1.172 0.82 -250
1.2 1.2 0.87
1.224 1.228 0.92 250
V V V nA ms
FBP Fault Trip Point FBP Input Bias Current FBP Effective Transconductance
50
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FN7523.2 September 21, 2005
EL7585A
Electrical Specifications
PARAMETER VDD = 5V, VBOOST = 11V, ILOAD = 200mA, VON = 15V, VOFF = -5V, VLOGIC = 2.5V, over temperature from -40C to 85C, unless otherwise specified. (Continued) CONDITION I(VON) = 0mA to 20mA VFBP = 1.1V, VDRVP = 25V VFBP = 1.5V, VDRVP = 35V IDRVN = 0.2mA, TA = 25C IDRVN = 0.2mA VF_FBN IFBN GMN VOFF/ I(VOFF) IDRVN IL_DRVN VLOGIC LDO VFBL VF_FBL IFBL GML VLOGIC/ I(VLOGIC) IDRVL IL_DRL SEQUENCING tON tSS tDEL1 tDEL2 tDEL3 IDELB CDEL tFAULT OT IPG Turn On Delay Soft-start Time Delay Between AVDD and VOFF Delay Between VON and VOFF Delay Between VOFF and Delayed VBOOST DELB Pull-down Current CDLY = 0.22F CDLY = 0.22F CDLY = 0.22F CDLY = 0.22F CDLY = 0.22F VDELB > 0.6V VDELB < 0.6V Delay Capacitor 10 FAULT DETECTION Fault Time Out Over-temperature Threshold PG Pull-down Current VPG>0.6V VPG<0.6V LOGIC ENABLE VHI VLO Logic High Threshold Logic Low Threshold 2.2 0.8 V V CDLY = 0.22F 50 140 15 1.7 ms C A mA 30 2 10 17 10 50 1.4 220 ms ms ms ms ms A mA nF FBL Regulation Voltage IDRVL = 1mA, TA = 25C IDRVL = 1mA FBL Fault Trip Point FBL Input Bias Current FBL Effective Transconductance VLOGIC Load Regulation DRVL Sink Current Max IL_DRVL VFBL falling VFBL = 1.35V VDRVL = 2.5V, IDRVL = 1mA to 8mA I(VLOGIC) = 100mA to 500mA VFBL = 1.1V, VDRVL = 2.5V VFBL = 1.5V, VDRVL = 5.5V 8 1.176 1.174 0.82 -500 200 0.5 16 0.1 5 1.2 1.2 0.87 1.224 1.226 0.92 500 V V V nA ms % mA A FNN Fault Trip Point FBN Input Bias Current FBN Effective Transconductance VOFF Load Regulation DRVN Source Current Max DRVN Leakage Current VFBN rising VFBN = 0.2V VDRVN = -6V, IDRVN = 0.2mA to 2mA I(VOFF) = 0mA to 20mA VFBN = 0.3V, VDRVN = -6V VFBN = 0V, VDRVN = -20V 2 0.173 0.171 0.38 -250 50 -0.5 4 0.1 5 2 MIN TYP -0.5 4 0.1 5 MAX UNIT % mA A
DESCRIPTION
VON/I(VON) VON Load Regulation IDRVP IL_DRVP VOFF LDO VFBN FBN Regulation Voltage DRVP Sink Current Max DRVP Leakage Current
0.203 0.203 0.43
0.233 0.235 0.48 250
V V V nA ms % mA A
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FN7523.2 September 21, 2005
EL7585A
Electrical Specifications
PARAMETER ILOW IHIGH VDD = 5V, VBOOST = 11V, ILOAD = 200mA, VON = 15V, VOFF = -5V, VLOGIC = 2.5V, over temperature from -40C to 85C, unless otherwise specified. (Continued) CONDITION MIN TYP 0.2 at VEN = 5V 12 18 MAX 1 24 UNIT A A
DESCRIPTION Logic Low bias Current Logic High bias Current
Pin Descriptions
PIN NAME 1 2 3, 4 5 6 7 8 9, 17 10 11 12, 13 14 15 16 18 19 20 PIN NUMBER CDLY DELB LX1, LX2 DRVP FBP DRVL FBL SGND DRVN FBN PGND VREF CINT FBB EN VDD PG DESCRIPTION A capacitor connected from this pin to GND sets the delay time for start-up sequence and sets the fault timeout time Gate drive of optional VBOOST delay FET Drain of the internal N channel boost FET; for EL7586, pin 4 is not connected Positive LDO base drive; open drain of an internal N channel FET Positive LDO voltage feedback input pin; regulates to 1.2V nominal Logic LDO base drive; open drain of an internal N channel FET Logic LDO voltage feedback input pin; regulates to 1.2V nominal Low noise signal ground Negative LDO base drive; open drain of an internal P channel FET Negative LDO voltage feedback input pin; regulates to 0.2V nominal Power ground, connected to source of internal N channel boost FET Bandgap voltage bypass, connect a 0.1F to SGND VBOOST integrator output, connect capacitor to SGND for PI mode or connect to VDD for P mode operation Boost regulator voltage feedback input pin; regulates to 1.2V nominal Enable pin, High=Enable; Low or floating=Disable Positive supply Gate drive of optional fault protection FET, when chip is disabled or when a fault has been detected, this is high
Typical Performance Curves
100 90 80 EFFICIENCY (%) 60 50 40 30 20 10 0 0 0.1 0.2 0.3 IOUT (A) 0.4 0.5 0.6 VO=15V EFFICIENCY (%) 70 VO=12V VO=9V 100 90 80 70 60 50 40 30 20 10 0 0 0.5 IOUT (A) 1 1.5 VO=15V VO=9V VO=12V
FIGURE 1. VBOOST EFFICIENCY AT VIN=3V (PI MODE)
FIGURE 2. VBOOST EFFICIENCY AT VIN=5V (PI MODE)
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EL7585A Typical Performance Curves
100 90 80 EFFICIENCY (%) 60 50 40 30 20 10 0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 VO=15V VO=12V EFFICIENCY (%) 70 VO=9V
(Continued)
100 90 80 70 60 50 40 30 20 10 0 0 0.5 IOUT (A) 1 1.5 VO=15V VO=12V
VO=9V
IOUT (A)
FIGURE 3. VBOOST EFFICIENCY AT VIN=3V (P MODE)
FIGURE 4. VBOOST EFFICIENCY AT VIN=5V (P MODE)
0 -0.1 -0.2 -0.3 -0.4 -0.5 VO=12V 0 0.1 0.2 0.3 IOUT (A) 0.4 0.5 0.6 VO=9V VO=15V
0 -0.1 VO=9V -0.2 -0.3 -0.4 -0.5 -0.6 VO=15V 0 0.2 0.4 0.6 0.8 IOUT (A) 1 1.2 1.4 VO=12V
LOAD REGULATION (%)
FIGURE 5. VBOOST LOAD REGULATION AT VIN=3V (PI MODE)
FIGURE 6. VBOOST LOAD REGULATION AT VIN=5V (PI MODE)
0 -1 LOAD REGULATION (%) -2 -3 -4 -5 -6 -7 -8 0 0.2 VO=12V 0.4 IOUT (A) 0.6 0.8 VO=15V VO=9V LOAD REGULATION (%)
LOAD REGULATION (%)
0 -2 -4 -6 -8 VO=15V -10 0 0.5 IOUT (A) 1 1.5 VO=12V
VO=9V
FIGURE 7. VBOOST LOAD REGULATION AT VIN=3V (P MODE)
FIGURE 8. VBOOST LOAD REGULATION AT VIN=5V (P MODE)
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EL7585A Typical Performance Curves
0 LOAD REGULATION (%) LOAD REGULATION (%) 0 20 40 IOUT (mA) 60 80 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6
(Continued)
0 -0.2 -0.4 -0.6 -0.8 -1 -1.2 -1.4 0 20 40 60 80 100
IOUT (mA)
FIGURE 9. VON LOAD REGULATION
FIGURE 10. VOFF LOAD REGULATION
0 LOAD REGULATION (%) -0.2 -0.4 VCDLY -0.6 VLOGIC -0.8 -1 -1.2 VIN EN 0 100 200 300 400 500 600 700 TIME (10ms/DIV) CDLY=220nF
IOUT (mA)
FIGURE 11. VLOGIC LOAD REGULATION
FIGURE 12. START-UP SEQUENCE
VCDLY VLOGIC VIN VREF CDLY=220nF
AVDD VLOGIC VOFF
VON
CDLY=220nF
TIME (10ms/DIV)
TIME (10ms/DIV)
FIGURE 13. START-UP SEQUENCE
FIGURE 14. START-UP SEQUENCE
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FN7523.2 September 21, 2005
EL7585A Typical Performance Curves
(Continued)
AVDD VLOGIC VOFF VIN=5V VOUT=13V IOUT=30mA TIME (400ns/DIV)
VON
CDLY=220nF
TIME (10ms/DIV)
FIGURE 15. START-UP SEQUENCE
FIGURE 16. LX WAVEFORM - DISCONTINUOUS MODE
0.8 0.7 POWER DISSIPATION (W) 0.6 0.5 0.4 0.3 0.2 0.1 VIN=5V VOUT=13V IOUT=200mA TIME (400ns/DIV) 0
JEDEC JESD51-3 AND SEMI G42-88 (SINGLE LAYER) TEST BOARD 714mW 667mW QFN24 JA=140C/W QFN16 JA=150C/W
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (C)
FIGURE 17. LX WAVEFORM - CONTINUOUS MODE
FIGURE 18. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
3 POWER DISSIPATION (W) 2.5 2 1.5 1 0.5 0
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD - QFN EXPOSED DIEPAD SOLDERED TO PCB PER JESD51-5 2.703W 2.500W QFN24 JA=37C/W
QFN16 JA=40C/W
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (C)
FIGURE 19. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
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FN7523.2 September 21, 2005
EL7585A
VREF REFERENCE
OSCILLATOR COMP OSC LX BUFFER
SLOPE COMPENSATION FBB GM AMPLIFIER CINT VOLTAGE AMPLIFIER
PWM LOGIC CONTROLLER
CURRENT AMPLIFIER UVLO COMPARATOR CURRENT REF CURRENT LIMIT COMPARATOR SS + VREF BUFFER
PGND
SHUTDOWN & START-UP CONTROL THERMAL SHUTDOWN
DRVP
FBP UVLO COMPARATOR SS + SS + BUFFER
DRVN BUFFER FBN 0.4V
0.2V
VREF
DRVL
FBL UVLO COMPARATOR UVLO COMPARATOR
FIGURE 20. BLOCK DIAGRAM
Applications Information
The EL7585A is a highly integrated multiple output power solution for TFT-LCD applications. The system consists of one high efficiency boost converter and three linearregulator controllers (VON, VOFF, and VLOGIC) with multiple protection functions. A block diagram is shown in Figure 20. Table 1 lists the recommended components. The EL7585A integrates an N-channel MOSFET boost converter to minimize external component count and cost. The AVDD, VON, VOFF, and VLOGIC output voltages are independently set using external resistors. VON, VOFF voltages require external charge pumps which are post regulated using the integrated LDO controllers.
TABLE 1. RECOMMENDED COMPONENTS DESIGNATION C1, C2, C3 C20, C31 DESCRIPTION 10F, 16V X5R ceramic capacitor (1206) TDK C3216X5R0J106K 4.7F, 25V X5R ceramic capacitor (1206) TDK C3216X5R1A475K
TABLE 1. RECOMMENDED COMPONENTS (Continued) DESIGNATION D1 DESCRIPTION 1A 20V low leakage Schottky rectifier (CASE 45704) ON SEMI MBRM120ET3
D11, D12, D21 200mA 30V Schottky barrier diode (SOT-23) Fairchild BAT54S L1 Q1 Q4 Q3 Q2 Q5 6.8H 1.3A Inductor TDK SLF6025T-6R8M1R3-PF -2.4 -20V P-channel 1.8V specified PowerTrench MOSFET (SuperSOT-3) Fairchild FDN304P -2A -30V single P-channel logic level PowerTrench MOSFET (SuperSOT-3) Fairchild FDN360P 200mA 40V PNP amplifier (SOT-23) Fairchild MMBT3906 200mA 40V NPN amplifier (SOT-23) Fairchild MMBT3904 1A 30V PNP low saturation amplifier (SOT-23) Fairchild FMMT549
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EL7585A
Boost Converter
The main boost converter is a current mode PWM converter at a fixed frequency of 1MHz which enables the use of low profile inductors and multilayer ceramic capacitors. This results in a compact, low cost power system for LCD panel design. The EL7585A is designed for continuous current mode, but they can also operate in discontinuous current mode at light load. In continuous current mode, current flows continuously in the inductor during the entire switching cycle in steady state operation. The voltage conversion ratio in continuous current mode is given by:
A VDD 1 --------------- = -----------1-D V IN
An external resistor divider is required to divide the output voltage down to the nominal reference voltage. Current drawn by the resistor network should be limited to maintain the overall converter efficiency. The maximum value of the resistor network is limited by the feedback input bias current and the potential for noise being coupled into the feedback pin. A resistor network in the order of 60k is recommended. The boost converter output voltage is determined by the following equation:
R1 + R2 A VDD = -------------------- x V REF R1
The current through the MOSFET is limited to 3.5A peak. This restricts the maximum output current based on the following equation:
V IN I L I OMAX = I LMT - -------- x -------- 2 VO
Where D is the duty cycle of the switching MOSFET. Figure 21 shows the block diagram of the boost regulator. It uses a summing amplifier architecture consisting of GM stages for voltage feedback, current feedback and slope compensation. A comparator looks at the peak inductor current cycle by cycle and terminates the PWM cycle if the current limit is reached.
Where IL is peak to peak inductor ripple current, and is set by:
V IN D I L = --------- x ---L fS
where fS is the switching frequency.
CLOCK SLOPE COMPENSATION
SHUTDOWN & START-UP CONTROL
Ifb CURRENT AMPLIFIER PWM LOGIC BUFFER
Iref
LX
Ifb FBB GM AMPLIFIER
Iref
VOLTAGE AMPLIFIER REFERENCE GENERATOR
CINT
PGND
FIGURE 21. BLOCK DIAGRAM OF THE BOOST REGULATOR
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EL7585A
The following table gives typical values (margins are considered 10%, 3%, 20%, 10%, and 15% on VIN, VO, L, fS, and IOMAX:
TABLE 2. VIN (V) 3.3 3.3 3.3 5 5 5 VO (V) 9 12 15 9 12 15 L (H) 6.8 6.8 6.8 6.8 6.8 6.8 fS (MHz) 1 1 1 1 1 1 IOMAX 1.040686 0.719853 0.527353 1.576797 1.090686 0.79902
capacitor. The voltage rating of the output capacitor should be greater than the maximum output voltage.
NOTE: Capacitors have a voltage coefficient that makes their effective capacitance drop as the voltage across them increases. COUT in the equation above assumes the effective value of the capacitor at a particular voltage and not the manufacturer's stated value, measured at zero volts.
Compensation
The EL7585A can operate in either P mode or PI mode. Connecting the CINT pin directly to VIN will enable P mode; For better load regulation, use PI mode with a 4.7nF capacitor in series with a 10K resistor between CINT and ground. This value may be reduced to improve transient performance, however, very low values will reduce loop stability.
Input Capacitor
An input capacitor is used to supply the peak charging current to the converter. It is recommended that CIN be larger than 10F. The reflected ripple voltage will be smaller with larger CIN. The voltage rating of input capacitor should be larger than maximum input voltage.
Boost feedback resistors
As the boost output voltage, AVDD, is reduced below 12V the effective voltage feedback in the IC increases the ratio of voltage to current feedback at the summing comparator because R2 decreases relative to R1. To maintain stable operation over the complete current range of the IC, the voltage feedback to the FBB pin should be reduced proportionally, as AVDD is reduced, by means of a series resistor-capacitor network (R7 and C7) in parallel with R1, with a pole frequency (fp) set to approximately 10kHz for C2 effective = 10F and 4kHz for C2 (effective) = 30F. R7 = ((1/0.1 x R2) - 1/R1)^-1 C7 = 1/(2 x 3.142 x fp x R7)
Boost Inductor
The boost inductor is a critical part which influences the output voltage ripple, transient response, and efficiency. Values of 3.3H to 10H are to match the internal slope compensation. The inductor must be able to handle the following average and peak current:
IO I LAVG = -----------1-D I L I LPK = I LAVG + -------2
PI mode CINT (C23) and RINT (R10)
The IC is designed to operate with a minimum C23 capacitor of 4.7nF and a minimum C2 (effective) = 10F. Note that, for high voltage AVDD, the voltage coefficient of ceramic capacitors (C2) reduces their effective capacitance greatly; a 16V 10F ceramic can drop to around 3F at 15V. To improve the transient load response of AVDD in PI mode, a resistor may be added in series with the C23 capacitor. The larger the resistor the lower the overshoot but at the expense of stability of the converter loop - especially at high currents. With L = 10H, AVDD = 15V, C23 = 4.7nF, C2 (effective) should have a capacitance of greater than 10F. RINT (R7) can have values up to 5k for C2 (effective) up to 20F and up to 10K for C2 (effective) up to 30F. Larger values of RINT (R7) may be possible if maximum AVDD load currents less than the current limit are used. To ensure AVDD stability, the IC should be operated at the maximum desired current and then the transient load response of AVDD should be used to determine the maximum value of RINT.
Rectifier Diode
A high-speed diode is necessary due to the high switching frequency. Schottky diodes are recommended because of their fast recovery time and low forward voltage. The rectifier diode must meet the output current and peak inductor current requirements.
Output Capacitor
The output capacitor supplies the load directly and reduces the ripple voltage at the output. Output ripple voltage consists of two components: the voltage drop due to the inductor ripple current flowing through the ESR of output capacitor, and the charging and discharging of the output capacitor.
V O - V IN IO 1 V RIPPLE = I LPK x ESR + ----------------------- x --------------- x ---VO C OUT f S
For low ESR ceramic capacitors, the output ripple is dominated by the charging and discharging of the output
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EL7585A
Cascaded MOSFET Application
A 20V N-channel MOSFET is integrated in the boost regulator. For the applications where the output voltage is greater than 20V, an external cascaded MOSFET is needed as shown in Figure 22. The voltage rating of the external MOSFET should be greater than VBOOST.
VIN VBOOST
The base-emitter saturation voltage is: Vbe_max = 1.25V (note this is normally a Vbe ~ 0.7V, however, for the Q5 transistor an internal Darlington arrangement is used to increase it's current gain, giving a 'base-emitter' voltage of 2 x VBE). (Note that using a high current Darlington PNP transistor for Q5 requires that VIN > VLOGIC + 2V. Should a lower input voltage be required, then an ordinary high gain PNP transistor should be selected for Q5 so as to allow a lower collector-emitter saturation voltage). For the EL7585A, the minimum drive current is: I_DRVL_min = 8mA The minimum base-emitter resistor, RBL, can now be calculated as: RBL_min = VBE_max/(I_DRVL_min - Ic/Hfe_min) = 1.25V/(8mA - 500mA/100) = 417
LX FB EL7585A
FIGURE 22. CASCADED MOSFET TOPOLOGY FOR HIGH OUTPUT VOLTAGE APPLICATIONS
Linear-Regulator Controllers (VON, VLOGIC, and VOFF)
The EL7585A includes three independent linear-regulator controllers, in which two are positive output voltage (VON and VLOGIC), and one is negative. The VON, VOFF, and VLOGIC linear-regulator controller functional diagrams, applications circuits are shown in Figures 23, 24, and 25 respectively.
This is the minimum value that can be used - so, we now choose a convenient value greater than this minimum value; say 500. Larger values may be used to reduce quiescent current, however, regulation may be adversely affected, by supply noise if RBL is made too high in value.
VBOOST 0.1F 0.9V PG_LDOP + LDO_ON 36V ESD CLAMP CP (TO 36V) RBP 7k DRVP FBP + GMP 1: Np RP1 RP2 20k 0.1F Q3 VON (TO 35V) CON LX
Calculation of the Linear Regulator Base-Emitter Resistors (RBL, RBP and RBN)
For the pass transistor of the linear regulator, low frequency gain (Hfe) and unity gain freq. (fT) are usually specified in the datasheet. The pass transistor adds a pole to the loop transfer function at fp=fT/Hfe. Therefore, in order to maintain phase margin at low frequency, the best choice for a pass device is often a high frequency low gain switching transistor. Further improvement can be obtained by adding a base-emitter resistor RBE (RBP, RBL, RBN in the Functional Block Diagram), which increase the pole frequency to: fp=fT*(1+ Hfe *re/RBE)/Hfe, where re=KT/qIc. So choose the lowest value RBE in the design as long as there is still enough base current (IB) to support the maximum output current (IC). We will take as an example the VLOGIC linear regulator. If a Fairchild FMMT549 PNP transistor is used as the external pass transistor, Q5 in the application diagram, then for a maximum VLOGIC operating requirement of 500mA the data sheet indicates Hfe_min = 100.
FIGURE 23. VON FUNCTIONAL BLOCK DIAGRAM
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EL7585A
LX 0.1F
CP (TO -26V) LDO_OFF PG_LDON 0.4V + FBN 1: Nn + GMN 36V ESD CLAMP VREF RN2 20k 0.1F
RN1 VOFF (TO -20V) DRVN RBN 3k Q2 COFF
consists of an external diode-capacitor charge pump powered from the inductor (LX) of the boost converter, followed by a low dropout linear regulator (LDO_OFF). The LDO_OFF regulator uses an external NPN transistor as the pass element. The onboard LDO controller is a wide band (>10MHz) transconductance amplifier capable of 4mA drive current, which is sufficient for up to 40mA or more output current under the low dropout condition (forced beta of 10). Typical VOFF voltage supported by EL7585A ranges from -5V to -20V. A fault comparator is also included for monitoring the output voltage. The undervoltage threshold is set at 200mV above the 0.2V reference level. The VLOGIC power supply is used to power the logic circuitry within the LCD panel. The DC-DC may be powered directly from the low voltage input, 3.3V or 5.0V, or it may be powered through the fault protection switch. The LDO_LOGIC regulator uses an external PNP transistor as the pass element. The onboard LDO controller is a wide band (>10MHz) transconductance amplifier capable of 16mA drive current, which is sufficient for up to 160mA or more output current under the low dropout condition (forced beta of 10). Typical VLOGIC voltage supported by EL7585A ranges from +1.3V to VDD-0.2V. A fault comparator is also included for monitoring the output voltage. The undervoltage threshold is set at 25% below the 1.2V reference.
FIGURE 24. VOFF FUNCTIONAL BLOCK DIAGRAM
VIN OR VPROT (3V TO 6V) 0.9V PG_LDOL + LDO_LOG RBL 500 Q5 DRVL RL1 FBL + GML 1: N1 RL2 20k VLOGIC (1.3V TO 3.6V) CLOG 10F
Set-Up Output Voltage
Refer to the Typical Application Diagram, the output voltages of VON, VOFF, and VLOGIC are determined by the following equations:
R 12 V ON = V REF x 1 + --------- R 11 R 22 V OFF = V REFN + --------- x ( V REFN - V REF ) R
21
FIGURE 25. VLOGIC FUNCTIONAL BLOCK DIAGRAM
R 42 V LOGIC = V REF x 1 + --------- R 41
The VON power supply is used to power the positive supply of the row driver in the LCD panel. The DC-DC consists of an external diode-capacitor charge pump powered from the inductor (LX) of the boost converter, followed by a low dropout linear regulator (LDO_ON). The LDO_ON regulator uses an external PNP transistor as the pass element. The onboard LDO controller is a wide band (>10MHz) transconductance amplifier capable of 4mA drive current, which is sufficient for up to 40mA or more output current under the low dropout condition (forced beta of 10). Typical VON voltage supported by EL7585A ranges from +15V to +36V. A fault comparator is also included for monitoring the output voltage. The under-voltage threshold is set at 25% below the 1.2V reference. The VOFF power supply is used to power the negative supply of the row driver in the LCD panel. The DC-DC 12
Where VREF = 1.2V, VREFN = 0.2V. Resistor networks in the order of 250k, 120k and 10k are recommended for VON, VOFF and VLOGIC, respectively.
Charge Pump
To generate an output voltage higher than VBOOST, single or multiple stages of charge pumps are needed. The number of stage is determined by the input and output voltage. For positive charge pump stages:
V OUT + V CE - V INPUT N POSITIVE ------------------------------------------------------------V INPUT - 2 x V F
where VCE is the dropout voltage of the pass component of the linear regulator. It ranges from 0.3V to 1V depending on
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EL7585A
the transistor. VF is the forward-voltage of the charge pump rectifier diode. The number of negative charge pump stages is given by:
V OUTPUT + V CE N NEGATIVE -----------------------------------------------V INPUT - 2 x V F
Discontinuous/Continuous Boost Operation and its Effect on the Charge Pumps
The EL7585A VON and VOFF architecture uses LX switching edges to drive diode charge pumps from which LDO regulators generate the VON and VOFF supplies. It can be appreciated that should a regular supply of LX switching edges be interrupted, for example during discontinuous operation at light AVDD boost load currents, then this may affect the performance of VON and VOFF regulation depending on their exact loading conditions at the time. To optimize VON/VOFF regulation, the boundary of discontinuous/continuous operation of the boost converter can be adjusted, by suitable choice of inductor given VIN, VOUT, switching frequency and the AVDD current loading, to be in continuous operation. The following equation gives the boundary between discontinuous and continuous boost operation. For continuous operation (LX switching every clock cycle) we require that: I(AVDD_load) > D*(1-D)*VIN/(2*L*FOSC) where the duty cycle, D = (AVDD - VIN)/AVDD
To achieve high efficiency and low material cost, the lowest number of charge pump stages which can meet the above requirements, is always preferred.
High Charge Pump Output Voltage (>36V) Applications
In the applications where the charge pump output voltage is over 36V, an external npn transistor need to be inserted into between DRVP pin and base of pass transistor Q3 as shown in Figure 26; or the linear regulator can control only one stage charge pump and regulate the final charge pump output as shown in Figure 27.
CHARGE PUMP VIN OUTPUT OR AVDD 7k DRVP Q3 VON
NPN CASCODE TRANSISTOR
EL7585A
For example, with VIN = 5V, FOSC = 1.0MHz and AVDD = 12V we find continuous operation of the boost converter can be guaranteed for: L = 10H and I(AVDD) > 61mA
FBP
L = 6.8H and I(AVDD) > 89mA L = 3.3H and I(AVDD) > 184mA
Charge Pump Output Capacitors
FIGURE 26. CASCODE NPN TRANSISTOR CONFIGURATION FOR HIGH CHARGE PUMP OUTPUT VOLTAGE (>36V)
Ceramic capacitors with low ESR are recommended. With ceramic capacitors, the output ripple voltage is dominated by the capacitance value. The capacitance value can be chosen by the following equation:
I OUT C OUT -----------------------------------------------------2 x V RIPPLE x f OSC
LX 0.1F 0.1F 7k DRVP 0.47F EL7585A Q3 0.1F 0.1F VON 0.1F (>36V) AVDD
where fOSC is the switching frequency.
Start-Up Sequence
Figure 28 shows a detailed start-up sequence waveform. For a successful power-up, there should be six peaks at VCDLY. When a fault is detected, the device will latch off until either EN is toggled or the input supply is recycled. When the input voltage (VDD) exceeds 2.5V, VREF and VLOGIC turn on. At the same time, if EN is tied to VDD, an internal current source starts to charge CDLY to an upper threshold using a fast ramp followed by a slow ramp. If EN is low at this point, the CDLY ramp will be delayed until EN goes high. The first four ramps on CDLY (two up, two down) are used to initialize the fault protection switch and to check whether
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FBP
0.22F
FIGURE 27. THE LINEAR REGULATOR CONTROLS ONE STAGE OF CHARGE PUMP
13
EL7585A
there is a fault condition on CDLY or VREF. If a fault is detected, the outputs and the input protection will turn off, but VREF will stay on. If no fault is found, CCDLY continues ramping up and down. During the second ramp, the device checks the status of VREF and over temperature. At the peak of the second ramp, PG output goes low and enables the input protection PMOS Q1. Q1 is a controlled FET used to prevent in-rush current into VBOOST before VBOOST is enabled internally. Its rate of turn on is controlled by Co. When a fault is detected, M1 will turn off and disconnect the inductor from VIN. With the input protection FET on, NODE1 (See Typical Application Diagram) will rise to ~VIN. Initially the boost is not enabled so VBOOST rises to VIN-VDIODE through the output diode. Hence, there is a step at VBOOST during this part of the start-up sequence. If this step is not desirable, an external PMOS FET can be used to delay the output until the boost is enabled internally. The delayed output appears at AVDD. For EL7585A, VBOOST soft-start at the beginning of the third ramp. The soft-start ramp depends on the value of the CDLY capacitor. For CDLY of 220nF, the soft-start time is ~2ms. VOFF turns on at the start of the fourth peak. At the fifth peak, DELB gate goes low to turn on the external PMOS Q4 to generate a delayed VBOOST output. VON is enabled at the beginning of the sixth ramp. AVDD, PG, VOFF, DELB and VON are checked at end of this ramp. CINT has an internal current-limited clamp to keep the voltage within its normal range. If CINT is shorted low, the boost regulator will attempt to regulate to 0V. If CINT is shorted H, the regulator switches to P mode. If any of the regulated outputs (VBOOST, VON, VOFF or VLOGIC) are driven above their target levels the drive circuitry will switch off until the output returns to its expected value. If VBOOST is excessively loaded, the current limit will prevent damage to the chip. While in current limit, the part acts like a current source and the regulated output will drop. If the output drops below the fault threshold, a ramp will be initiated on CDELAY and, provided that the fault is sustained, the chip will be disabled on completion of the ramp. In some circumstances, (depending on ambient temperature and thermal design of the board), continuous operation at current limit may result in the over-temperature threshold being exceeded, which will cause the part to disable immediately. All I/O also have ESD protection, which in many cases will also provide overvoltage protection, relative to either ground or VDD. However, these will not generally operate unless abs max ratings are exceeded.
Component Selection for Start-Up Sequencing and Fault Protection
The CREF capacitor is typically set at 220nF and is required to stabilize the VREF output. The range of CREF is from 22nF to 1F and should not be more than five times the capacitor on CDEL to ensure correct start-up operation. The CDEL capacitor is typically 220nF and has a usable range from 47nF minimum to several microfarads - only limited by the leakage in the capacitor reaching A levels. CDEL should be at least 1/5 of the value of CREF (See above). Note with 220nF on CDEL the fault time-out will be typically 50ms and the use of a larger/smaller value will vary this time proportionally (e.g. 1F will give a fault time-out period of typically 230ms).
Fault Protection
During the startup sequence, prior to BOOST soft-start, VREF is checked to be within 20% of its final value and the device temperature is checked. If either of these are not within the expected range, the part is disabled until the power is recycled or EN is toggled. If CDELAY is shorted low, then the sequence will not start, while if CDELAY is shorted H, the first down ramp will not occur and the sequence will not complete. Once the start-up sequence is completed, the chip continuously monitors CDLY, DELB, FBP, FBL, FBN, VREF, FBB and PG and checks for faults. During this time, the voltage on the CDLY capacitor remains at 1.15V until either a fault is detected, or the EN pin is pulled low. A fault on CDELAY, VREF or temperature will shut down the chip immediately. If a fault on any other output is detected, CDELAY will ramp up linearly with a 5A (typical) current to the upper fault threshold (typically 2.4V), at which point the chip is disabled until the power is recycled or EN is toggled. If the fault condition is removed prior to the end of the ramp, the voltage on the CDLY capacitor returns to 1.15V. Typical fault thresholds for FBP, FBL, FBN and FBB are included in the tables. PG and DELB fault thresholds are typically 0.6V.
Fault Sequencing
The EL7585A has an advanced fault detection system which protects the IC from both adjacent pin shorts during operation and shorts on the output supplies. A high quality layout/design of the PCB, in respect of grounding quality and decoupling is necessary to avoid falsely triggering the fault detection scheme - especially during start-up. The user is directed to the layout guidelines and component selection sections to avoid problems during initial evaluation and prototype PCB generation.
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EL7585A
AVDD SOFT-START
FAULT DETECTED NORMAL OPERATION
VON SOFT-START
VREF, VLOGIC ON
VCDLY
VIN EN VREF
VBOOST tON tOS VLOGIC
VOFF
tDEL1 DELAYED VBOOST
VOFF ON
tDEL2 VON tDEL3
START-UP SEQUENCE TIMED BY CDLY
FIGURE 28. START-UP SEQUENCE
15
FAULT PRESENT
CHIP DISABLED
PG ON
DELB ON
FN7523.2 September 21, 2005
EL7585A
Over-Temperature Protection
An internal temperature sensor continuously monitors the die temperature. In the event that the die temperature exceeds the thermal trip point of 140C, the device will shut down. 6. The exposed die plate, on the underneath of the package, should be soldered to an equivalent area of metal on the PCB. This contact area should have multiple via connections to the back of the PCB as well as connections to intermediate PCB layers, if available, to maximize thermal dissipation away from the IC. 7. To minimize the thermal resistance of the package when soldered to a multi-layer PCB, the amount of copper track and ground plane area connected to the exposed die plate should be maximized and spread out as far as possible from the IC. The bottom and top PCB areas especially should be maximized to allow thermal dissipation to the surrounding air. 8. A signal ground plane, separate from the power ground plane and connected to the power ground pins only at the exposed die plate, should be used for ground return connections for feedback resistor networks (R1, R11, R41) and the VREF capacitor, C22, the CDELAY capacitor C7 and the integrator capacitor C23. 9. Minimize feedback input track lengths to avoid switching noise pick-up. A two-layer demo board is available to illustrate the proper layout implementation. A four-layer demo board can be used to further optimize the layout recommendations.
Layout Recommendation
The device's performance including efficiency, output noise, transient response and control loop stability is dramatically affected by the PCB layout. PCB layout is critical, especially at high switching frequency. There are some general guidelines for layout: 1. Place the external power components (the input capacitors, output capacitors, boost inductor and output diodes, etc.) in close proximity to the device. Traces to these components should be kept as short and wide as possible to minimize parasitic inductance and resistance. 2. Place VREF and VDD bypass capacitors close to the pins. 3. Minimize the length of traces carrying fast signals and high current. 4. All feedback networks should sense the output voltage directly from the point of load, and be as far away from LX node as possible. 5. The power ground (PGND) and signal ground (SGND) pins should be connected at only one point near the main decoupling capacitors.
Demo Board Layout
FIGURE 29. TOP LAYER
FIGURE 30. BOTTOM LAYER
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FN7523.2 September 21, 2005
EL7585A Typical Application Diagram
LX VIN Q1 C0 1nF NODE 1 C1 10F x2 C7 C10 4.7F R6 C6 R7 NODE 1 C41 10 4.7F 10k EN VREF DRVP FBP DRVL R42 5.4k R41 5k DRVN FBN SGND PGND R22 R21 20K VREF 104K C20 4.7F FBL R23 3k Q2 C25 0.1F D21 VOFF (-5V) R12 R11 20k 0.22F DELB VDD CINT R10 C 23 10k CP 4.7nF 1nF C13 0.1F C14 Q3 230k C15 0.47F C24 LX 0.1F 0.1F D12 C12 0.1F D11 VON (15V) LX C11 0.1F PG CDELAY LX FBB L1 6.8H D1 46.5k R2 R9 C2 10F 1M X2 R7 OPEN C7 OPEN C16 22nF R8 10k Q4 C9 0.1F AVDD (12V)
R1 5k
0.1F VREF C22 0.1F
R13 7k
R43 500 Q5 VLOGIC (2.5V) C 31 4.7F
NOTE: The SGND should be connected to the exposed die plate and connected to the PGND at one point only.
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FN7523.2 September 21, 2005
EL7585A QFN Package Outline Drawing
NOTE: The package drawing shown here may not be the latest version. To check the latest revision, please refer to the Intersil website at http://www.intersil.com/design/packages/index.asp
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 18
FN7523.2 September 21, 2005

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